In a nonvolatile semiconductor memory device disclosed in Japanese Patent Application Publication No. 2001-344986, an external read Y gate YGE and an internal operation Y gate YGI are arranged opposite to each other at opposite sides in the column direction of a memory cell array MA in each bank. The external read Y gate YGE couples a selected column of the memory cell array MA with the external read sense amplifier 150 through an internal data transmission line 400, according to a column select signal supplied from an external read column decoder EXCD. The internal operation Y gate YGI couples a selected column of the memory cell array MA to a write circuit and an internal verify sense amplifier 250 through an internal data transmission line 420, in accordance with a column select signal supplied from an internal operation column decoder INCD. This configuration helps increase the degree of freedom in arranging the write circuit, internal verify sense amplifier 250 and external read sense amplifier 150.
Other related technologies of such nonvolatile memory device are disclosed in Japanese Patent Application Publication Hei. 10-242433 and Japanese Patent Application Publication No. 2001-67868.
However, in the above-described related art, a function in which, when an internal operation such as erase/write is carried out with respect to one memory block, access is made to the other memory blocks to read data therefrom is realized while commonly providing a write circuit and a sense amplifier with respect to a predetermined number of banks and simplifying the layout of the column selection circuit, thereby reducing chip area.
In addition, the related art does not describe the power source lines for supplying a power source voltage or/and ground lines in a circuit for carrying out a rewrite operation of erasing/writing, as an internal operation, and a circuit for carrying out an operation to read out data to the exterior, and does not disclose the related configurations of the power source lines or/and ground lines.
In a nonvolatile memory device having a plurality of memory blocks, the read operation and rewrite operation are carried out asynchronously between the memory blocks. For this reason, there may be cases that the read operation and the rewrite operation are carried out simultaneously. If the read operation in which a micro-signal must be amplified by a sense amplifier and the rewrite operation in which a boost voltage or/and negative voltage must be generated and a rewrite high-voltage stress is applied to a memory cell are carried out simultaneously, a problem arises that voltage fluctuations caused by the rewrite operation may become a noise source with respect to the read operation. For instance, charging/discharging of a nonvolatile-specific boost voltage or/and negative voltage of 9V/−9V produces an extremely large power source noise with respect to the sensitivity, at an initial phase of the operation, of a 1.8V external power source and a sense amplifier to be used at the time of the read operation.
Further, the above-described related art does not disclose the positional relationship between the circuit for carrying out the rewrite operation and the circuit for carrying out the read operation. If the write circuit 250 and the sense amplifier 150 are arranged close to each other, as shown in FIG. 7, to thus reduce chip area, a problem arises that malfunctions of the read system circuit may occur due to voltage fluctuations in the write system circuit which become a noise source.